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|Title:||Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory||Author(s):||Zhao, Yingchao||Author(s):||Liu, T.
Xue, C. J.
|Issue Date:||2013||Publisher:||IEEE||Journal:||IEEE Transactions on Signal Processing||Volume:||61||Issue:||14||Start page:||3509||End page:||3520||Abstract:||
Phase change random access memory (PRAM) is one kind of nonvolatile memory, which is desirable to be used for DSP systems as main memory, as it consumes less power than DRAM and is much denser than DRAM. In this paper, we utilize a hybrid main memory composed of DRAM and PRAM, which leverages the low power consumption of PRAM while minimizing the performance and lifetime degradation caused by PRAM write. To make full use of different advantages of DRAM and PRAM, especially for the application-specific DSP systems, we reconsider the variable partitioning and instruction scheduling problems on the hybrid main memory. Different optimization objectives, for example power consumption, schedule length, and the number of writes on PRAM, are considered. At the same time, different kinds of hybrid architectures are analyzed. Graph models, ILP model, and algorithms are proposed for different settings. Experiments show that the proposed techniques reduce up to 49% power consumption and 88% the number of writes on PRAM on average.
|URI:||https://repository.cihe.edu.hk/jspui/handle/cihe/988||DOI:||10.1109/TSP.2013.2261295||CIHE Affiliated Publication:||Yes|
|Appears in Collections:||CIS Publication|
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