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Title: Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
Author(s): Zhao, Yingchao 
Author(s): Hu, J.
He, Y.
Zhuge, Q.
Sha, E. H.-M.
Xue, C. J.
Issue Date: 2013
Publisher: Elsevier
Journal: Journal of Systems Architecture 
Volume: 59
Issue: 7
Start page: 389
End page: 399
In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is to take advantage of locality as much as possible and integrate it into task scheduling. Two algorithms are proposed to optimize memory accesses while scheduling tasks with timing and resource constraints. The first one uses Integer Linear Programming (ILP) to produce a schedule with the most efficient memory access sequence while satisfying the constraints. The second one is a heuristic algorithm which can produce a near optimal schedule with polynomial running time. The experimental results show that the memory access cost can be reduced up to 60% while the schedule length is also shortened.
DOI: 10.1016/j.sysarc.2013.05.003
CIHE Affiliated Publication: Yes
Appears in Collections:CIS Publication

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