Please use this identifier to cite or link to this item: https://repository.cihe.edu.hk/jspui/handle/cihe/983
Title: Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
Author(s): Zhao, Yingchao 
Author(s): Hu, J.
He, Y.
Zhuge, Q.
Sha, E. H.-M.
Xue, C. J.
Issue Date: 2013
Publisher: Elsevier
Journal: Journal of Systems Architecture 
Volume: 59
Issue: 7
Start page: 389
End page: 399
Abstract: 
In multi-core Digital Signal Processing (DSP) Systems, the processor-memory gap remains the primary obstacle in improving system performance. This paper addresses this bottleneck by combining task scheduling and memory accesses so that the system architecture and memory modules of a multi-core DSP can be utilized as efficiently as possible. To improve the system and memory utilization, the key is ...
URI: https://repository.cihe.edu.hk/jspui/handle/cihe/983
DOI: 10.1016/j.sysarc.2013.05.003
CIHE Affiliated Publication: Yes
Appears in Collections:CIS Publication

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