Please use this identifier to cite or link to this item: https://repository.cihe.edu.hk/jspui/handle/cihe/993
DC FieldValueLanguage
dc.contributor.authorZhao, Yingchaoen_US
dc.contributor.otherHu, J.-
dc.contributor.otherXue, C. J.-
dc.contributor.otherTseng, W.-C.-
dc.contributor.otherZhuge, Q.-
dc.contributor.otherSha, E. H.-M.-
dc.date.accessioned2021-07-21T09:41:25Z-
dc.date.available2021-07-21T09:41:25Z-
dc.date.issued2012-
dc.identifier.urihttps://repository.cihe.edu.hk/jspui/handle/cihe/993-
dc.description.abstractThe growing gap between microprocessor speed and DRAM speed is a major problem that computer designers are facing. In order to narrow the gap, it is necessary to improve DRAM’s speed and throughput. To achieve this goal, this paper proposes techniques to take advantage of the characteristics of the 3-stage access of contemporary DRAM chips by grouping the accesses of the same row together and interleaving the execution of memory accesses from different banks. A family of Bubble Filling Scheduling (BFS) algorithms are proposed in this paper to minimize memory access schedule length and improve memory access time for embedded systems. When the memory access trace is known in some application-specific embedded systems, this information can be fully utilized to generate efficient memory access schedules. The offline BFS algorithm can generate schedules which are 47.49% shorter than in-order scheduling and 8.51% shorter than existing burst scheduling on average. When memory accesses are received by the single memory controller in real time, the memory accesses have to be scheduled as they come. The online BFS algorithm in this paper serves this purpose and generates schedules which are 58.47% shorter than in-order scheduling and 4.73% shorter than burst scheduling on average. To improve the memory throughput and further reduce the memory access schedule, an architecture with dual memory controllers is proposed. According to the experimental results, the dual controller algorithm can generate schedules which are 62.89% shorter than in-order scheduling, 14.23% shorter than burst scheduling, and 10.07% shorter than single controller BFS algorithms on average.en_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.relation.ispartofJournal of Systems Architectureen_US
dc.titleMemory access schedule minimization for embedded systemsen_US
dc.typejournal articleen_US
dc.identifier.doi10.1016/j.sysarc.2011.10.002-
dc.contributor.affiliationSchool of Computing and Information Sciencesen_US
dc.relation.issn1383-7621en_US
dc.description.volume58en_US
dc.description.issue1en_US
dc.description.startpage48en_US
dc.description.endpage59en_US
dc.cihe.affiliatedYes-
item.languageiso639-1en-
item.openairetypejournal article-
item.grantfulltextopen-
item.fulltextWith Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_6501-
item.cerifentitytypePublications-
crisitem.author.deptSchool of Computing and Information Sciences-
crisitem.author.orcid0000-0001-8362-6735-
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